An FPGA implementation of Walsh-Hadamard transforms for signal processing

This paper describes two approaches suitable for an FPGA implementation of Walsh-Hadamard transforms. These transforms are important in many signal-processing applications including speech compression, filtering and coding. Two novel architectures for the Fast Hadamard Transforms using both systolic architecture and distributed arithmetic techniques are presented. The first approach uses the Baugh-Wooley multiplication algorithm for a systolic architecture implementation. The second approach is based on both distributed arithmetic ROM and accumulator structure, and a sparse matrix factorisation technique. Implementations of the algorithms on a Xilinx FPGA board are described. Distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.